Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - VHDL fifo

Search list

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] sdh

Description: 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform
Platform: | Size: 6144 | Author: liu | Hits:

[VHDL-FPGA-Verilog] vhdl0716

Description: ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
Platform: | Size: 8431616 | Author: 杨奋燕 | Hits:

[VHDL-FPGA-Verilog] tx

Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send.
Platform: | Size: 7168 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

[VHDL-FPGA-Verilog] generalFIFO

Description: 通用FIFO的VHDL编程 字深和字长可以自己设计
Platform: | Size: 1024 | Author: danny | Hits:

[Software Engineering] multiplier_8bit

Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Platform: | Size: 46080 | Author: 刘强 | Hits:

[Communication-Mobile] uart

Description: 这个是UART的控制器，已经跑通过，分4个模块，波特率生成、发送、接收和fifo,可供初学者参考-This is the UART controller, has been run through, sub-4 module, baud rate generating, sending, receiving and fifo, for beginners reference
Platform: | Size: 3072 | Author: duan | Hits:

[USB develop] cmos_fifo_usb

Description: cmos数据到fifo再到usb的fifo部分程序(68013a)-cmos data to fifo the fifo to the usb part of the procedures (68013a)
Platform: | Size: 158720 | Author: | Hits:

[Other Embeded program] 416fifosource

Description: FIFO电路Verilog实现 -FIFO circuit realize Verilog
Platform: | Size: 3072 | Author: Jerry | Hits:

[VHDL-FPGA-Verilog] fifo-

Description:
Platform: | Size: 143360 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] 37724082FIFO

Description: 基于Verilog HDL的异步FIFO设计与实现-Verilog HDL-based Asynchronous FIFO Design and Implementation
Platform: | Size: 3072 | Author: 汤奥 | Hits:

[VHDL-FPGA-Verilog] fifo8x9

Description: 8位深，9位宽FIFO VHDL源码设计，如需改进可在此基础上扩展-8 deep, 9-bit wide FIFO VHDL source design, for improving on this basis can be extended
Platform: | Size: 1024 | Author: lxy | Hits:

[VHDL-FPGA-Verilog] asyn_FIFOandFPGAdesign

Description: 一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article
Platform: | Size: 453632 | Author: Roger | Hits:

[VHDL-FPGA-Verilog] hdl

Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Platform: | Size: 6144 | Author: 刘义春 | Hits:

[OS Develop] CliffordECummingsFIFO

Description: 超值奉献，Clifford E. Cummings FIFO关于异步FIFO的两篇文章，同时附有中文解说，主要讲解异步FIFO的实现难点---空满标志的产生，以及读写地址的产生-Value dedication, Clifford E. Cummings FIFO asynchronous FIFO on the two articles, at the same time accompanied with a Chinese guide, mainly on the realization of asynchronous FIFO difficult--- the emergence of space-age logo, as well as read and write addresses generated
Platform: | Size: 227328 | Author: horse | Hits:

[USB develop] usb

Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD
Platform: | Size: 4731904 | Author: 李华 | Hits:

[MPI] v2_fifo_vhd_258

Description: 这是一个基于xilinx ISE9.1的一个历程，包含两个FIFO代码，第一个FIFO读写用同一个时钟，第二个FIFO读写用不同的时钟。-This is a xilinx ISE9.1 based on a course code consists of two FIFO, the first FIFO read and write using the same clock, the second FIFO read and write with a different clock.
Platform: | Size: 92160 | Author: muerqing | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
Platform: | Size: 1106944 | Author: xiao cao | Hits:
« 1 2 3 4 5 6 78 9 10 11 12 ... 18 »

CodeBus www.codebus.net